Chinese Chipmakers Pay Higher Prices as EUV Ban Forces Repeated Exposures

Chinese semiconductor firms face rising costs and lower yields as they manufacture advanced chips without extreme ultraviolet lithography machines. Export controls have prevented ASML from shipping its EUV equipment to China, forcing manufacturers to rely on older deep ultraviolet tools. This reliance requires exposing critical chip layers multiple times to build complex circuits. Industry experts note that this method introduces more defects and extends production timelines.

ASML is the sole producer of EUV machines, which use 13.5-nanometer wavelength light to print fine features. Analysts estimate the technological gap between China and Western rivals in this area is at least five years. Despite these constraints, Chinese firms have made notable strides in chip density using available equipment.

SMIC produced the Kirin 9000S processor for Huawei’s Mate 60 Pro in 2023 without EUV. The chip used a second-generation 7-nanometer class process. Recent analysis suggests SMIC has advanced its DUV-based process to densities closer to 5-nanometer manufacturing standards. However, the company still lags behind TSMC and Samsung in overall process density.

The technique involves multiple patterning. Manufacturers split intricate designs into simpler patterns and apply them sequentially. Chris Mack, co-founder and CTO of Fractilia, explains that the question of whether a chip can be made without EUV ignores the financial trade-offs. Industry standards suggest three exposures on a 193 immersion tool cost roughly the same as one EUV exposure. At four masks, EUV becomes the more economical choice.

Precision is critical in this process. Each new pattern must align exactly with previous etchings. More exposures lead to accumulated overlay errors and process variation. Designers often add extra space around features to compensate for these errors. This enlargement reduces the number of dies per wafer, a costly outcome when wafers cost tens of thousands of dollars. Mack states, "You don't sell wafers, you sell die."

Morgan Stanley estimates that Chinese DRAM maker CXMT produces only about one-third as many bits per wafer as its Western competitors. The bank calls lithography access a hard ceiling for Chinese memory development. Mack adds that node labels like 5-nanometer or 3-nanometer have limited meaning on their own. He notes that SMIC's N+3 process, while a step forward, remains less scaled than established 5-nanometer processes from Samsung and TSMC.

DUV technology still has potential. Micron developed its 1-alpha DRAM without EUV using tight process control. Mack says Micron pushed 193-nanometer tools farther than other memory makers. Morgan Stanley believes CXMT can achieve its planned move to 1-alpha DRAM for HBM3e without EUV. Douglas Fuller, a researcher at Copenhagen Business School, expects advanced packaging to allow DUV use for the latest DRAM generations by the end of the decade.

Micron eventually adopted EUV for its 1-gamma DRAM. The company reports this technology delivers more than 30 percent greater bit density per wafer than the previous 1-beta generation. Mack says he would be hard pressed to believe a 3-nanometer or 2-nanometer node could be economically viable without EUV. EUV has its own challenges, including stochastic effects that require higher exposure doses.

Chinese chipmakers plan to continue pushing DUV limits. They accept larger dies, poorer yields, and longer manufacturing times to maintain production. Morgan Stanley projects CXMT will lift its share of global DRAM bit supply from 14 percent in 2026 to 16 percent in 2028 through new capacity. The bank also expects China's AI chip self-sufficiency to rise from 42 percent in 2025 to 70 percent by 2030.

EUV, HBM, and advanced software will continue to define the gap between Chinese and Western chip capabilities. Chinese firms are adding new greenfield capacity to offset efficiency losses. The industry relies on these DUV workarounds to sustain growth in the interim.